The present disclosure relates to a substrate bonding method, and more specifically to the formation of bumps using an adhesive resin, and to bonding a substrate using these bumps.
Methods for mounting chips on substrates known as “flip-chip techniques,” in which the bottom surface of a die and a substrate are connected via bumps arranged in the form of an array, are conventionally well-known. Among these techniques, the widely used controlled collapse chip connection (C4) technique, which uses solder balls as bumps. In the C4 technique, the solder bumps on the electrode pads on the bottom surface of the die are aligned with the substrate terminals, the solder is then melted, and the electrode pads on the bottom of the die are now connected electrically to the substrate terminals. Finally, the gap between the substrate and the die are filled with an under fill agent to secure the die.
However, these solder bumps have become finer as chips have become more highly integrated, and the pitch has become narrower. As a result, the gap between chips and substrates has narrowed, and under fill agents have become difficult to use.
In order to ensure that there is a sufficient gap between chips and substrates, the use of Cu pillar bumps which form solder bumps on copper columns (pillars) formed using a plating technique has been studied. However, there is a problem with these Cu pillar bumps.
First, the elastic modulus of copper is more than three times that of solder materials, and the yield stress is more than eight times that of solder materials. As a result, the thermal stress that occurs when a chip is bonded to a substrate (for example, the stress that occurs due to the difference in thermal expansion coefficients between a silicon chip and an organic substrate) cannot be sufficiently buffered. As a result, the chip is subjected to a significant amount of thermal stress, and cracks develop in wiring layers using dielectric interlayer insulating film which has low mechanical strength. This decreases yields. Second, copper pillar bumps are formed using electrolytic plating, which causes a variation in the height of the bumps. As a result, the bonding ability of the bumps and substrate terminals becomes unstable. These problems have been exacerbated by finer pitches.